1. Field of the Invention
The present invention relates to microprocessor testing, and more particularly to an apparatus and method for controlling an input/output (I/O) clock for an integrated circuit (IC) during test during test which runs the IC under test at optimum core clock frequencies using test equipment with limited system bus capabilities.
2. Description of the Related Art
On most integrated circuit testers, and more particularly those which are employed to test microprocessor devices, the device under test is inserted into a test fixture which simulates and monitors input/output (I/O) signals of the device to determine if it is working properly. In the case of a microprocessor, for example, the tester generates and monitors all of the I/O signals that are required to interface the microprocessor to remaining components within a computer system. One skilled in the art will appreciate that the core frequency at which a present day microprocessor operates is a multiple of the frequency of the bus clock frequency that is provided by a conventional tester. In addition, one skilled in the art will appreciate that present day testers are limited in terms of the speed at which they can generate and monitor those signals interfaced to the microprocessor. For example, a present day system bus (e.g., front side bus in an x86-compatible microprocessor) operates at speeds up to 800 megahertz (MHz), yet present day low-cost testers are only able to provide for system bus speeds up to 400 MHz. The tester is primary configured to test the core circuitry of the integrated circuit (IC) or microprocessor at the highest frequency possible rather than the I/O interface for the system bus, which may be properly tested with other means.
Thus, if a 50 MHz bus clock signal is generated by a tester to a microprocessor under test that is designed to respond to bus clock frequencies up to 100 MHz, then provisions must be made in the design of the microprocessor to enable its core logic to operate at full speed during test. In present day systems, techniques for doing this include providing for clock frequency ratio values that are enabled and exclusively employed during test. To illustrate, consider a microprocessor that is designed to accept a 100 MHz bus clock signal with a maximum clock ratio value equal to 32 in which the value 32 is used to multiply the frequency of the bus clock. At the high end, the processor is designed to operate at up to 3.2 gigahertz (GHz). But with a 50 MHz bus clock signal that is generated by a tester, the maximum obtainable core clock speed is 1.6 GHz using the clock ratio of 32. Accordingly, one approach to increasing the core speed of the microprocessor of this example is to increase the clock ratio value to 64, which can be enabled and specified only during test. Thus, when a 50 MHz bus clock signal is provided by a tester, the multiplier of 64 is employed to increase the internal core clock speed up to 3.2 GHz.
The conventional approach for increasing the core clock frequency of a device under test is problematic from several standpoints. First, the present inventor has noted that advances in the art to provide for faster core clock frequencies have driven designers to employ logic elements and circuits within these devices which are highly tuned to a range of conditions surrounding the optimum. In the case of a device that derives an internal core clock as an integral multiple in frequency of an externally provided bus clock, phase-locked loop (PLL) circuits are employed that are designed to provide spectrally pure core clocks within the range of clock multiples provided for by the device. For example, consider a microprocessor that is designed to accept a 100 MHz bus clock and to generate a core clock up to a multiple of 32. The particular PLL that is employed thus operates optimally for clock multiples up to 32. Now, one skilled in the art will appreciate, as does the present inventor, that most present day PLL circuits will allow for increasing the clock multiplier beyond this value such that higher core clock frequencies can be provided responsive to lower frequency bus clock signals. But it has been observed that pushing the PLL circuits in this manner is disadvantageous because the resulting core clocks exhibit spectral impurities (e.g., jitter) which, when applied to sensitive internal logic devices, may cause failures of the device under test that are due only to the degraded core clock that is being generated in a non-optimal region of multiples for a given PLL.
It is desired to test an IC, including microprocessors, at optimum core clock speeds using a frequency limited bus clock provided by a tester to which the IC is coupled.